The field of invention relates generally to micro-fabrication of structures. More particularly, the present invention is directed to forming patterned substrates suitable for use in damascene processes.
Micro-fabrication involves the fabrication of very small structures, e.g., having features on the order of micro-meters or smaller. One area in which micro-fabrication has had a sizeable impact is in the processing of integrated circuits. As the semiconductor processing industry continues to strive for larger production yields while increasing the circuits per unit area formed on a substrate, micro-fabrication becomes increasingly important. Micro-fabrication provides greater process control, while allowing increased reduction of the minimum feature dimension of the structures formed.
A common process employed during the manufacturing of integrated circuits involves fabrication of metal conductive lines and contacts. The contacts interconnect adjacent conductive lines separated by a insulative layer. Conductive lines and contacts are often fabricated by forming a stepped structure in a substrate, referred to as a via and a trench. A common means by which to form the via-trench stepped structure is known as the damascene process.
Damascene involves forming grooves in an insulating layer and filling the same with a conductive material, such as aluminum, copper and the like. In this manner, conductive lines are formed in the groove. To form the contacts, as well as the conductive lines, a dual damascene process is typically employed to form a via in the region of the insulating layer in which the groove is formed.
An exemplary dual damascene process patterns, on the insulating layer, an image pattern of a via. To that end, the insulating layer is coated with a photo-resist and exposed through an appropriate mask which is then exposed to form the image pattern of the vias. The pattern is anisotropically etched in the upper portion of the insulating layer. The photo-resist is then exposed through a second mask with an image pattern of the grooves, after being aligned with the first mask pattern to encompass the vias. Anisotropically etching the grooves for the conductive lines in the upper portion of the insulating material results in the via, already present in the upper portion of the insulating layer, being simultaneously etched and replicated in the lower portion of the insulating material. After the etching is complete, both the vias and grooves are filled with a conductive material metal. Simultaneously filling both the grooves and vias with conductive material is an improvement over the single damascene process. However, the dual damascene process is attendant with disadvantages such as requiring alignment between two different masks. In addition, to increase process time and cost required by two mask steps, alignment becomes critical to properly position the groove with respect to the via.
There is a need, therefore, to provide improved processes for forming stepped structures in furtherance of the fabrication of integrated circuits.